The present invention relates to an improved regulator circuit and in particular to an improved regulator circuit for a back bias generator for an MOS integrated circuit.
It has become common to use a back bias generator circuit with dynamic MOS circuits. A back bias generator applies a negative voltage on the "back" or substrate of an MOS integrated circuit. Without a back bias generator the normal voltage for the substrate is zero volts. This back or substrate bias is used to reduce device body effect and parasitic junction capacitance. This has the effect of insuring more reliable switching of the internal MOS logic elements. One such back bias generator is described in an article entitled "THPM 12.6: A 70-ns 1K MOS RAM" by Pashley and McCormick, 1976 IEEE International Solid-State Circuits Conference, pp. 138-139, 238.
Existing back bias generators typically sense only two parameters, V.sub.TE and V.sub.BB. The former is the threshold voltage. This refers to the voltage difference between the gate and the source required to change the state of the MOS element. V.sub.TE must be exceeded for it to become fully conducting. V.sub.BB stands for the back-bias voltage applied to the substrate. For example if V.sub.TE should happen to increase then this is sensed; the back-bias is increased, i.e. made less negative; and as a result, the MOS element becomes more sensitive to an incoming clock pulse than it would otherwise be.
These methods compress the variation range of V.sub.TE and effectively tighten the circuit processing limits. But they do not compensate for insufficient clock amplitude and other important circuit parameters.